Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Accurately assessing the power consumption of an electronic circuit is increasingly important with the proliferation of battery powered devices. However, some approaches may significantly underestimate or overestimate the power needs of a device. Approaches for estimating the power consumption that are not based on simulation of the circuit design rely on probabilistic measures for the inputs and the switching activities (“toggle rates”). The toggle rate is the rate at which a net or logic element changes state compared to its input(s). For synchronous elements, the toggle rate reflects how often an output changes relative to a given dock input.
Glitches could as much as double the toggle rate. A glitch is spurious transient output of a combinational circuit and can be caused by delays of internal signals in a combinational circuit such that the state of the output depends on the delays. As the input signals may not arrive at the same time for generating the output signal, the state of the output signal can toggle until the input signals are stabilized. Power consumption may be significantly underestimated or overestimated depending on how glitches are handled.